1. Field of Invention
The present invention relates, in general, to signal processing, and more specifically to a method and system for improving quality of audio sound.
2. Background
Hearing aids and similar listening devices typically include a DSP having hearing aid algorithms, a sigma-delta modulator, a H-bridge output driver, and a hearing aid transducer. The DSP runs from an internal oscillator at some configured frequency that is typically in the range of 1 to 10 MHz but may be higher or lower. The sigma-delta modulator is clocked from the internal oscillator. The sigma-delta modulator is used to generate modulated signals from a baseband audio signal. The H-bridge output driver outputs a pulse width modulated (PWM) signal used to drive the hearing aid transducer.
The problem occurs when an algorithm running on the DSP needs to increase the configured operating frequency. This may occur when the algorithm requires more processing cycles to complete its computation. One option for the algorithm would be to always run at the fastest required frequency. However the use of the fastest required frequency has the negative side effect of increased power consumption, even then it is not necessary, which may be unacceptable for battery powered devices (e.g., hearing aids or other listening devices).
Alternative option for the algorithm may be to increase and subsequently decrease the operating frequency in real-time (known as “clock throttling”). When a clock throttling event occurs, there is a potential for the PWM output signal going to the hearing aid transducer to become corrupt. The PWM output signal may become corrupt because the internal oscillator's clock period changes in such a way that cannot be compensated with through typical digital clock dividers. The corrupted PWM output signal results in an audio artifact audible to the hearing aid user. The artifact has been described as a ‘click’ or ‘pop’ sound. Such artifact is undesirable.
A hearing aid DSP being a low power device typically contains a basic free-running RC oscillator circuit for generating the clock and minimizing power consumption. When the frequency of the clock changes, the oscillator may lack phase compensation to save power and thus the generated clock is subjected to a potential phase error during the oscillator adjustment. Such a phase error can cause audio artifacts. To reducing the audio artifacts, the DSP's internal oscillator itself may be improved. However, the problem may occur because the internal oscillator will transition from the high-to-low or low-to-high operating frequency in a non-zero amount of time. During this transition event a PWM output signal must remain coherent. The clock period between edge transitions needs to remain constant to eliminate the artifact.
Accordingly, it is desirable to have a method and system that allows for clock frequency changes without inducing audio artifacts.